The typical startup sequence of a pulse width modulation (PWM) DC to DC converter is to ramp the non-inverted or positive input of a feedback control error amplifier from zero volts to a target set point voltage level. The error amplifier is part of the feedback control loop which regulates an output voltage by comparing the reference voltage with a feedback signal based on a sensed portion of the output voltage. In an exemplary buck type converter, the PWM control circuitry provides a PWM signal which controls a gate driver, which further controls a switching device pair to convert an input voltage to the regulated output voltage. The switching device pair includes an upper switching device and a lower switching device which are typically implemented as a MOSFET pair.
If the converter is started up into a pre-biased load, such as when the output voltage is already charged, there can be large potentially damaging transient currents because the reference voltage is less than the feedback signal. In particular, since the feedback loop attempts to regulate the output voltage by comparing the voltage level of the feedback signal based on the output voltage with the reference voltage at the input of the error amplifier, where the feedback signal is already high and the reference voltage is ramping up at startup, the control circuit attempts to pull the output voltage lower by turning on the “pull down” output switching device (e.g., the lower device of the switching device pair). In this situation, the lower device can be turned on long enough to exceed its thermal limit. The surge currents can cause significant stress to on-chip components possibly resulting in catastrophic failure. In addition, these surge currents are “non-monotonicities” or variations in the output voltage which in some cases can cause downstream integrated circuits to latch up and fail.
Modern buck voltage regulator specifications require monotonic startup in the presence of pre-biased outputs. Monotonic startup is difficult in applications with pre-biased outputs as existing startup methods result in an average voltage across the output inductor that is not 0 volts which in turn causes current to build up in the inductor according to the equation DV=L*DI/DT. This build up of current in the conductor causes a non-monotonicity on the output voltage of the regulator as the control loop stabilizes.
To mitigate this problem previous prior art has utilized an accurate analog multiplier architecture, which requires a BICMOS process to identify an initial PWM duty cycle whose purpose is to make the average voltage across the output inductor equal to 0 volts. A CMOS process may also be used but will have a much lower quality. This requires the use of BJT's to implement a Gilbert Multiplier. Implementing this in various products using various types of processes is difficult as these processes frequently do not have the types of transistors necessary to design an analog multiplier of the requisite accuracy. Additionally, the design must allow for operation over a wide operating frequency and input/output voltage ranges. Other previous art utilizes simple less effective solutions including startup after two PWM pulses (effectively at 1% duty cycle), startup at 50% duty cycle, or operating the regulator non-synchronously to prevent negative current in the inductor. These methods have several drawbacks and are inferior solutions to that described herein below.